Thick bond pad for chip with cavity package

ABSTRACT

Disclosed herein a method, including depositing a silicon nitride layer over an inter layer dielectric (ILD); depositing a first conductive layer having a first thickness; forming a mask over a first portion of the first conductive layer to expose a second portion of the first conductive layer; etching the first conductive layer; etching the silicon nitride layer with a fluorine-based etch; and depositing a second conductive layer having a second thickness.

FIELD OF THE INVENTION

This invention relates generally to chips with a cavity package and moreparticularly to a thick bond pad for chips with a cavity package.

BACKGROUND

Chips with cavity packages have a similar structure to a conventionalchip with the exception that a portion of the lid or cover glass of thepackage is offset from the surface of the chip, forming a cavity. Acommon application for chips with cavity packages is for image sensorchips commonly used in such devices as cell phones. The cavity of imagesensor chips contains components including micro lenses, color filters,and sensors in the cavity. In the case of an image sensor chip, a glasslayer is placed over the front side of the image sensor chip, with apolymer spacer between the glass and the image sensor chip, around theperimeter of the array. Note that the polymer spacer is absent from thearray. This structure protects the components placed in the cavity whilesimultaneously allowing light to reach the components.

Referring to FIG. 1, the polymer layer 14 that forms the cavity 16prevents connective wiring (i.e. such as a wire bond) access to the topwiring layer 12. Referring to FIG. 2, in order to access the top wiringlayer 12, after the chip is diced, package leads 26 are placed along theside of the chip that make lateral connections with the top wiringlayers 12. A bond pad 28 is the area of connection of the top wiringlayer 12 and the package lead 26. The bond pad 28, via the package lead26, connects the image sensor chip 2 to other circuits in the camera.

The top wiring layer is preferably thin—approximately less than one(1.0) micron. Thin top wiring layers maximize the image sensor chip'ssensitivity to light. At the same time, the lateral connections formedbetween the package leads on the side of the chip and the thin topwiring layers create connections with high resistance due to the smallcross-sectional area of the thin top wiring layers and the packageleads. Therefore, there is a conflict in the requirements of thethickness of the top wiring layer. On the one hand, thick top wiringlayers result in thick bond pads, of approximately one (1.0) micron ormore, permitting better package lead connections with lower resistance,while on the other hand, thin top wiring layers, of approximately lessthan one (1.0) micron, permit finely spaced and narrow wires.

BRIEF SUMMARY

A first aspect of the disclosure provides an image sensor chip,comprising a substrate having at least one via extending through atleast one inter layer dielectric (ILD); a first conductive layer overthe ILD, wherein the first conductive layer has a first thickness; asecond conductive layer over the first conductive layer, wherein thesecond conductive layer has a second thickness of less than the firstthickness; a polymer layer over the second conductive layer, the polymerlayer including a cavity; a plurality of cavity components in thecavity; and an optically transparent layer contacting the polymer layerand covering the cavity.

A second aspect of the disclosure provides chip with a cavity package,comprising: a substrate having at least one via extending through atleast one inter layer dielectric (ILD); a first conductive layer overthe ILD, wherein the first conductive layer has a first thickness; asecond conductive layer over the first conductive layer, wherein thesecond conductive layer has a second thickness of less than the firstthickness; a polymer layer over the second conductive layer, the polymerlayer including a cavity; and a protective layer contacting the polymerlayer and covering the cavity.

A third aspect of the disclosure provides a method, the methodcomprising: depositing a silicon nitride layer over an inter layerdielectric (ILD); depositing a first conductive layer having a firstthickness; forming a mask over a first portion of the first conductivelayer to expose a second portion of the first conductive layer; etchingthe first conductive layer; etching the silicon nitride layer with afluorine-based etch; and depositing a second conductive layer having asecond thickness.

These and other aspects, advantages and salient features of theinvention will become apparent from the following detailed description,which, when taken in conjunction with the annexed drawings, where likeparts are designated by like reference characters throughout thedrawings, disclose embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other aspects, features and advantages of the inventionwill be better understood by reading the following more particulardescription of the invention in conjunction with the accompanyingdrawings.

FIG. 1 shows a cross-section view of a known image sensor chip prior todicing.

FIG. 2 shows a cross-section view of a known image sensor chip afterdicing.

FIG. 3 shows a cross-section view of a known chip scale package.

FIG. 4 shows a cross-section view of one embodiment of an image sensorchip before dicing according to the invention.

FIG. 5 shows a cross-section view of one embodiment of an image sensorchip after dicing according to the invention.

FIG. 6 shows a cross-section view of one embodiment of a chip with acavity package after dicing according to the invention.

FIG. 7 shows a cross-section view of one embodiment of a step of formingan image sensor chip according to the invention.

FIG. 8 shows a cross-section view of one embodiment of a step of formingan image sensor chip according to the invention.

FIG. 9 shows a cross-section view of one embodiment of a step of formingan image sensor chip according to the invention.

FIG. 10 shows a cross-section view of one embodiment of a step offorming an image sensor chip according to the invention.

The drawings are not necessarily to scale. The drawings are merelyschematic representations, not intended to portray specific parametersof the invention. The drawings are intended to depict only typicalembodiments of the invention, and therefore should not be considered aslimiting the scope of the invention. In the drawings, like numberingrepresents like elements.

DETAILED DESCRIPTION

Referring to FIG. 1, a cross-section view of a known image sensor chip 2prior to dicing is shown. Image sensor chip 2 includes a substrate 4, aninter layer dielectric (ILD) 6 over substrate 4, a plurality of vias 8through ILD 6, a plurality of internal wiring layers 10 stacked withinILD 6, a conductive layer 12 over ILD 6 and connecting to plurality ofvias 8, a polymer layer 14 over conductive layer 12, a cavity 16 formedwithin polymer layer 14, a plurality of cavity components 18 (e.g.,micro lenses and color filters 20 connected to a sensor 22), and a glasslayer 24 contacting polymer layer 14 and covering cavity 16.

Referring to FIG. 2, a cross-section view of a known image sensor chip 2after dicing is shown. Dicing creates slanted sides. Polymer layer 14prevents connective wiring access to conductive layer 12. In order toprovide connective wiring access to conductive layer 12, after dicing,image sensor chip 2 includes a plurality of package leads 26 along theside of the image sensor chip 2 forming lateral connections withconductive layer 12. Image sensor chip 2 may include an insulator 40between package leads 26 and substrate 4 providing electrical isolationfrom the substrate 2. Insulator 46 may include silicon oxide (SiO₂),silicon nitride (SiN), or any other suitable material. A plurality ofbond pads 28 form lateral connections in areas where the conductivelayers 12 and package leads 26 contact. Package leads 26 run under imagesensor chip 2 to a plurality of bump pads 30. A plurality of solderballs 32 are connected to plurality of bump pads 30.

Referring to FIG. 3, a known chip scale package 34 is shown. Chip scalepackage 34 comprises image sensor chip 2, a logic chip 36 and a carrierpackage 38. Bond pads 28 connect conductive layer 12 with package leads28. Package leads 26 via the bump pads 30 and solder balls 32 connectimage sensor chip 2 to logic chip 36. Logic chip 36 is connected tocarrier package 38.

Referring to FIG. 4, a cross sectional view of one embodiment of animage sensor chip 102 before dicing in accordance with this invention isshown. While an image sensor chip 102 is illustrated, the teachings ofthe invention can be applicable to any chip with a cavity package suchas for use in a Micro-Electro-Mechanical Systems (MEMS). This embodimentincludes a substrate 104. Substrate 104 may be comprised of but notlimited to silicon, germanium, silicon germanium, silicon carbide, andthose consisting essentially of one or more Group III-V compoundsemiconductors having a composition defined by the formulaAl_(X1)Ga_(X2)In_(X3)AS_(Y1)P_(Y2)N_(Y3)Sb_(Y4), where X1, X2, X3, Y1,Y2, Y3, and Y4 represent relative proportions, each greater than orequal to zero and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 being the total relativemole quantity). Substrate 104 may also be comprised of Group II-VIcompound semiconductors having a compositionZn_(A1)Cd_(A2)Se_(B1)Te_(B2), where A1, A2, B1, and B2 are relativeproportions each greater than or equal to zero and A1+A2+B1+B2=1 (1being a total mole quantity). The processes to provide substrate 104, asillustrated and described, are well known in the art and thus, nofurther description is necessary. Transistors and other now known orlater developed devices may be included in the substrate 104. In oneembodiment, substrate 104 of image sensor chip 102 may include aphotodiode. Transistors and photodiodes are well known in the art andthus, no further description is necessary.

Image sensor chip 102 may include at least one inter layer dielectric(ILD) 106 over substrate 104. Any number of dielectric layers may belocated over the chip body, as may other layers included insemiconductor chips now known or later developed. In one embodiment, ILD106 may include silicon oxide (SiO₂) for its insulating, mechanical andoptical qualities. ILD 106 may include but are not limited to: siliconnitride (Si₃N₄), fluorinated SiO₂ (FSG), hydrogenated silicon oxycarbide(SiCOH), porous SiCOH, boro-phosho-silicate glass (BPSG),silsesquioxanes, carbon (C) doped oxides (i.e., organosilicates) thatinclude atoms of silicon (Si), carbon (C), oxygen (O), and/or hydrogen(H), thermosetting polyarylene ethers, SiLK (a polyarylene etheravailable from Dow Chemical Corporation), a spin-on silicon-carboncontaining polymer material available form JSR Corporation, other lowdielectric constant (<3.9) material, or layers thereof. Inter-leveldielectric layer 130 may be deposited using conventional techniquesdescribed herein and/or those known in the art.

As used herein, the term “deposition” may include any now known or laterdeveloped techniques appropriate for the material to be depositedincluding but are not limited to, for example: chemical vapor deposition(CVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD),semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapidthermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reactionprocessing CVD (LRPCVD), metalorganic CVD (MOCVD), sputteringdeposition, ion beam deposition, electron beam deposition, laserassisted deposition, thermal oxidation, thermal nitridation, spin-onmethods, physical vapor deposition (PVD), atomic layer deposition (ALD),chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

One embodiment of image sensor chip 102 includes at least one via 108through ILD 106. In one embodiment, at least one via 108 may includetungsten. At least one via 108 may also include copper, aluminum, gold,silicides, or any other now known or later developed suitable materials.A plurality of internal wiring layers 110 may be included in ILD 106.The internal wiring layers 110 may be comprised of copper or any othersuitable material.

One embodiment of image sensor chip 102 includes a first conductivelayer 140 positioned over ILD 106. First conductive layer 140 has afirst thickness. For example, first thickness may be approximately 1.0microns or greater. First conductive layer 140 may have a taperedprofile.

Continuing with FIG. 4, one embodiment of image sensor chip 102 includesa second conductive layer 142 positioned over first conductive layer140. Second conductive layer 142 has a second thickness of less than thefirst thickness. In one embodiment, second conductive layer 142 includesaluminum. For example, second thickness may be approximately less than1.0 microns. Second conductive layer 142 may also include gold orcopper. In embodiments where first conductive layer 140 and secondconductive layer 142 do not include the same material, an electricallyconducting diffusion barrier (not shown) of titanium nitride, tantalumnitride, tungsten, or any other suitable material may be includedbetween first conductive layer 140 and second conductive layer 142.Second conductive layer 142 forms a connection with at least one via 108and first conductive layer 140. Second conductive layer 142substantially conforms to the profile of the first conductive layer 140.In one embodiment, second conductive layer 142 may completely coverfirst conductive layer 140.

One embodiment of image sensor chip 102 includes a polymer layer 114positioned over second conductive layer 142. In one embodiment polymerlayer 114 may be applied by now known or later developed techniquesincluding spin-on or laminate techniques. Polymer layer 114 may includea photosensitive polymer such as benzocyclobutene (BCB) or any othersuitable material. Polymer layer 114 includes a cavity 116. Cavity 116may be formed by etching or by photolithographic processing (i.e., ifpolymer layer 114 is a photosensitive material). One embodiment of imagesensor chip 102 includes a plurality of cavity components 118 (e.g.,micro lenses and color filters 120 and sensor 122) in cavity 116 formedusing conventional techniques. An optically transparent layer 124 maycontact polymer layer 114 and covering cavity 116. Optically transparentlayer 124 allows light to reach cavity components 118 while protectingcavity components 118. In one embodiment, optically transparent layer124 may include glass.

Referring to FIG. 5, a cross sectional view of one embodiment of animage sensor chip 102 after dicing in accordance with this invention isshown. First conductive layer 140 and second conductive layer 142 form aconnection with a package lead 126. Together first conductive layer 140and second conductive layer 142 form a thick bond pad 144. Thick bondpad 144 is described as thick in comparison to known image sensor chips102 where bond pad 128 is of approximately the same thickness asconductive layer 112 of less than one (1.0) micron (see FIGS. 1 and 2).Package leads 126 run along the side of image sensor chip 102 to bumppads 130 and solder balls 132. The package leads 126 may be comprised ofgold, copper, aluminum or any other suitable material. In an embodimentwhere substrate 104 is comprised of conducting or semiconductingmaterial, package lead 126 may be isolated from substrate 104 by aninsulator 146 such as silicon oxide (SiO₂), silicon nitride (SiN), orany other suitable material. Image sensor chip 2 may then be connectedto a logic chip 36 and to a carrier package 38 using any now known orlater developed technique.

Referring to FIG. 6, a cross sectional view of one embodiment of a chipwith a cavity package 246 in accordance with this invention is shown.This embodiment includes a substrate 204; an inter layer dielectric(ILD) 206 over substrate 204; at least one via 208 through ILD 206; afirst conductive layer 240 over ILD 206, wherein first conductive layer240 has a first thickness; a second conductive layer 222 over firstconductive layer 240, wherein second conductive layer 242 has a secondthickness of less than the first thickness; a polymer layer 214 oversecond conductive layer 242, and polymer layer 214 including a cavity216. A person skilled in the art will readily recognize that cavity 216could be used to hold cavity components 218. One embodiment may includea protective layer 224 placed over the polymer layer 214 and cavity 216.In one embodiment, protective layer 124 may allow other types ofradiation such as x-rays or infrared radiation to reach cavitycomponents 218 while substantially protecting cavity components 118.

Referring to FIG. 7, a cross-section view of one embodiment of a step offorming image sensor chip 102 before etching according to the inventionis shown. Prior to this process, parts of image sensor chip 102 areformed on a substrate 104 including at least one inter layer dielectric(ILD) 106 deposited over substrate 104 and at least one via 108 throughILD 106 using any now known or later developed technique. A siliconnitride layer 148 is deposited over ILD 106. In one embodiment, siliconnitride layer 148 is deposited using PECVD. First conductive layer 140having first thickness is deposited over silicon nitride layer 148. Inone embodiment, silicon nitride layer 148 is deposited using CVD. In oneembodiment, first conductive layer includes aluminum. First conductivelayer may also include gold or copper. First thickness is approximately1.0 microns or greater. A mask 150 may be formed over a portion of firstconductive layer 140. Mask 150 may have a tapered profile or any othersuitable shape. In FIG. 7, first conductive layer 140 is etched. Firstconductive layer 140 may be etched using any now known or laterdeveloped technique.

In an embodiment that includes first conductive layer 140 comprised ofaluminum, a chlorine-based etch may be used. Chlorine-based etch mayinclude at least one of a reactive-ion etch and an isotropic etch. In anembodiment that includes first conductive layer 140 comprised of gold orcopper, a mask may be used for etching. Mask 150 may be formed using anorganic material (e.g., photoresist), a hardmask including an inorganicmaterial (e.g., silicon oxide (SiO₂), silicon nitride (SiN), or anyother suitable material), or any other now known or later developedtechnique. Referring to FIG. 8, a cross-section view of one embodimentof a step of forming an image sensor chip 102 after the etching of FIG.7 according to the invention is shown. Here, first conductive layer 140has been etched. Etching removes exposed portions of first conductivelayer 140 leaving unexposed portions of first conductive layer 140 witha profile similar in the shape of mask 150 (FIG. 7). In this way,silicon nitride layer 148 remains substantially intact during and afterthe etching. Silicon nitride layer 148 substantially protects at leastone via 108 from reacting with the etching.

In an embodiment that includes first conductive layer 140 comprised ofgold or copper, a selective electroplating process may be used.Selective electroplating process may include any now known or laterdeveloped technique. For example, selective electroplating process mayinclude depositing a seed layer (e.g., sputtered Ta/Cu). A resistpattern including openings may be formed over seed layer. Firstconductive layer 140 is deposited in openings of resist pattern. Resistpattern and seed layer are substantially removed using a wet or dry etchor any other suitable technique leaving first conductive layer 140.

Referring to FIG. 9, silicon nitride layer 148 is then etched with,e.g., a fluorine-based etch, substantially removing silicon nitridelayer 148. Silicon nitride layer 148 may remain under first conductivelayer 140. In this way, first conductive layer 140 and at least one via108 remain intact.

Referring to FIG. 10, second conductive layer 142 having a secondthickness is deposited and patterned over first conductive layer 140 andpartially over ILD 106. Second thickness is less than approximately 1.0microns. Second conductive layer 142 may be patterned using any nowknown or later developed techniques so as to form a connection with atleast one via 108 and first conductive layer 140. Second conductivelayer 142 may be etched to form a top wiring layer comprised of aplurality of wiring connections.

The method as described above is used in the fabrication of integratedcircuit chips. The resulting integrated circuit chips can be distributedby the fabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

While various embodiments are described herein, it will be appreciatedfrom the specification that various combinations of elements, variationsor improvements therein may be made by those skilled in the art, and arewithin the scope of the invention. In addition, many modifications maybe made to adapt a particular situation or material to the teachings ofthe invention without departing from essential scope thereof. Therefore,it is intended that the invention not be limited to the particularembodiment disclosed as the best mode contemplated for carrying out thisinvention, but that the invention will include all embodiments fallingwithin the scope of the appended claims.

What is claimed is:
 1. A method, comprising: depositing a siliconnitride layer over an inter layer dielectric (ILD); depositing a firstconductive layer having a first thickness; forming a mask over a firstportion of the first conductive layer to expose a second portion of thefirst conductive layer; etching the first conductive layer; etching thesilicon nitride layer with a fluorine-based etch; and depositing asecond conductive layer having a second thickness.
 2. The method ofclaim 1, wherein the first thickness is approximately 1.0 micron orgreater.
 3. The method of claim 1, wherein the second thickness is lessthan approximately 1.0 micron.
 4. The method of claim 1, furthercomprising connecting the first conductive layer and the secondconductive layer with a package lead.
 5. The method of claim 1, furthercomprising connecting the second conductive layer with the firstconductive layer and the at least one via in the ILD.
 6. The method ofclaim 1, wherein the second conductive layer depositing includescompletely covering the first conductive layer with the secondconductive layer.
 7. The method of claim 1, wherein the first conductivelayer is aluminum.
 8. The method of claim 7, wherein the etching thefirst conductive layer includes using a chlorine-based etching.